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32 gbps dual channel advanced linear equalizer data sheet hmc6545 rev. a document feedback information furnished by analog devices is believed to be accurate and reliable. howeve r, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or othe rwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2015 analog devices, inc. all rights reserved. technical support www.analog.com features supports data rates from dc up to 32 gbps protocol and data rate agnostic low latency (<170 ps) integrated agc with differential sensitivity of < 50 mv u p to 20 db programmable multi ple unit i n terval input equalization extend ed chromatic and polarization mode dispersion tolerance programmable d ifferential o utput a mplitude c ontrol of up to 600 mv single 3.3 v supply eliminating external regulators wide temperature range from ?40 c to + 95 c 5 mm 5 mm , 32- lead lfcsp package applications 40 g bps /100 g bps dqpsk direct detection receivers short and long reach cfp2 and qsfp+ m odules cei - 28g mr and cei - 25g lr 100 g e l ine c ard s 16 g bps and 32 g bps fibr e channel infiniband 14 g bps fdr and 28 g bps edr r ates signal c onditioning for b ackplane and l ine c ards broadband test and measurement equipment functional block dia gram figure 1. general description the hmc6545 is a low power, high performance, fully programmable , dual - channel , asynchronous advanced linear equalizer that operates at data rates of up to 32 gbps. the hmc6545 is protocol and data rate agnostic , and it can operate on the transmit path to predistort a transmitt ed signal to invert channel distortion or on the receiver path to equalize the distorted and attenuated received signal. the hmc6545 is effective in dealing with chromatic and polariz ation mode dispersion and inter symbol interference (isi) caused by a wide var iety of t ransmission media (backplane or fiber ) and channel lengths. the hmc6545 consists of an automatic gain control (agc) ; dc offset correction circuitry ; a 9 - tap , 18 ps spaced feed forward eq ualizer (ffe); a summing node; and a linear programmable output driver. the input agc linearly attenuates or amplifies the distorted input signal to generate a constant voltage at the input of the ffe. the 9 - tap ffe is programmed via 2 - wire interface to ge nerate wide range frequency responses that are precursor or postcursor in nature for compensating signal impairments. after ffe tap coefficients are summed at the summing node, the signal is received by a linear output driver. dc offset correction circuitr y is controlled either automatically or manually via forward error correction (fec). all high speed differential inputs and outputs of the hmc6545 are current mode logic ( cml ) and terminated on chip with 50 ? to the positive supply, 3.3 v, a n d can be dc - coupled or ac - coupled. the inputs and outputs of the hmc6545 can be operated either differentially or single - ended. the low power, hig h performance , and feature rich hmc6545 is packaged in a 5 mm 5 mm , 32- lead lfcsp package. the device uses a single 3.3 v supply , eliminating external regulators. the hmc6545 operates over a ?40c to +95c temperature range . 17 1 3 4 2 9 gnd inp0 inn0 gnd 5 6 gnd inp1 7 inn1 8 gnd gnd package base gnd 18 outn1 19 outp1 20 gnd 21 gnd 22 outn0 23 outp0 24 gnd cagc1 12 compn1 11 compp1 10 vcc1 13 sda 14 scl 15 svcc 16 vcc1 25 vcc0 26 regsel0 27 regsel1 28 rst 29 compn0 30 compp0 31 vcc0 32 cagc0 agc t/2 c0 t/2 c1 t/2 c2 t/2 t/2 t/2 t/2 t/2 cn d0 d1 d2 dn agc lpf lpf serial control registers hmc6545 13393-001
hmc6545 data sheet rev. a | page 2 of 23 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 g eneral description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 dc electrical characteristics ...................................................... 3 ac electrical characteristics ...................................................... 3 absolute maximum ratings ............................................................ 5 esd caution .................................................................................. 5 pin configuration and function descriptio ns ............................. 6 interface schematics ..................................................................... 7 typical performance characteristics ..............................................8 theory of operation ...................................................................... 11 input receiver ............................................................................. 11 ffe delay l ine ........................................................................... 11 output driver ............................................................................. 12 2 - wire serial port ....................................................................... 12 register map ................................................................................... 15 register list summary and register descri ptions ................ 15 evaluation printed circuit board (pcb) ..................................... 21 evaluation kit contents ............................................................ 21 outline dimensions ....................................................................... 23 ordering guide .......................................................................... 23 revision history 10 /15 revision a: initial version
data sheet hmc6545 rev. a | page 3 of 23 specifications dc electrical charac teristics unless otherwise noted , t ypical values at v cc = 3.3 v, t a = 25 c . table 1 . parameter symbol test conditions /comments min typ max unit p ower consumption supply voltage v cc 3.00 3.30 3.45 v supply current i ccmax single channel ; all tap amplifiers active 130 150 ma i ccmin single channel ; single - tap amplifier active 93 ma power - down supply current 17 ma dc offset correction at maximum agc gain automatic ? 60 + 60 mv manual ? 60 + 60 mv cml input port (inp0 , inn0, inp1 , inn1) input termination r in differential input resistance 80 100 120 cml output port (outp0 , outn0, outp1 , outn1) output termination r out single - ended output resistance 45 55 65 output level high v oh v cc v output v ol v cc ? 0.5 v cmos input (sda, scl, rst , regsel0, regsel1) input voltage level high v ih v cc ? 1.3 v input v il 0.8 v input current i il , i ih v il = 0 v or v ih = v cc ? 100 + 100 a ac electrical charac teristics unless otherwise noted , t ypical values at v cc = 3.3 v, t a = 25 c . table 2 . parameter test conditions/comments min typ max unit input data rate dc 32 gbps range differential input range for linear agc operation , thd < 5% 40 880 mv p -p input equalization 20 db differential amplitude input 40 1600 mv p -p output input signal: prbs 2 31 ? 1 at 100 mv p -p linear agc operation thd < 5% ; agc = 2 ; a ll taps enabled, tap 4 gain = 63, gain of all other taps = 0, predriver gain = 63 410 mv p -p agc = 7 600 mv p -p saturated agc operation all taps are enabled with maximum gain, p re d river g ain = 63, agc = 7 960 mv p -p agc settling time no external cap acitor 0.5 s ffe tap delay 18 ps delay depth 145 ps
hmc6545 data sheet rev. a | page 4 of 23 parameter test conditions/comments min typ max unit noise characteristics channel to channel isolation up to 32 ghz 30 db total harmonic distortion agc = 2, for differential input voltage 250 mv p -p 5 % output driver rise/fall time 20% to 80 % 16 p s additive rms jitter 1 input signal: 28 gbps, 1010 pattern ; a ll taps enabled, tap 4 gain = 63, gain of all other taps = 0, predriver gain = 63; agc = 2 0.4 ps latency 170 ps differential return loss up to 20 ghz input ?9 db output ?8 db number of taps 9 1 additive rms jitter is calculated by j rms,dut = ( ( j tested ) 2 ? ( j source ) 2 ) .
data sheet hmc6545 rev. a | page 5 of 23 absolute maximum rat ings table 3 . parameter rating v cc to gnd ? 0.6 v to +3.6 v all pins to gnd ?0.3 v to v cc + 0.3 v operating ambient temperature range ?40c to +95c differential peak -to - peak input voltage swing 1.6 v p -p maximum input voltage at cml inputs v cc + 0.6 v maximum input voltage at digital inputs (sda, scl, regsel1, regsel0, rst ) v cc + 0.6 v maximum peak reflow temperature 260c maximum junction temperature 125c continuous power dissipation (t a = 85 c , derate 46.59 mw/ c above 85 c) 1.86 w thermal resistance ( junction to epad) 21.46c/w esd sensitivity , human body model (hbm) class 1c stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. esd caut ion
hmc6545 data sheet rev. a | page 6 of 23 pin configuration an d function descripti ons figure 2 . pin configuration table 4 . pin function descriptions pin number mnemonic description 1, 4, 5, 8, 17, 20, 21, 24 gnd ground. this pin and the package base must be connected to rf and dc ground . 2, 3 inp0, inn0 differential cml inputs, channel 0 . 6, 7 inp1, inn1 differential cml inputs, channel 1. 9, 32 cagc1, cagc0 external capacitor for agc bandwidth. 10, 16 vcc1 power supplies for channel 1 . 11, 12 compp1, compn1 external capacitors to cancel dc offset, channel 1. 13 sda 2 - wire digital data. 14 scl 2 - wire digital clock. 15 svcc power supply for digital circuitry and bias. 18, 19 outn1, outp1 differential cml data outputs, channel 1. 22, 23 outn0, outp0 differential cml data outputs, channel 0. 25, 31 vcc0 power supplies for channel 0. 29, 30 compn0, compp0 external capacitors to cancel dc offset, channel 0. 26, 27 regsel0, regsel1 default coefficient selection for channel and 2 - wire interface device address. 28 rst reset for 2 - wire interface. epad exposed pad. the exposed pad must be connected to rf/dc ground . 17 1 3 4 2 9 gnd inp0 inn0 gnd 5 6 gnd inp1 7 inn1 8 gnd gnd package base gnd 18 outn1 19 outp1 20 gnd 21 gnd 22 outn0 23 outp0 24 gnd cagc1 12 compn1 11 compp1 10 vcc1 13 sda 14 scl 15 svcc 16 vcc1 25 vcc0 26 regsel0 27 regsel1 28 rst 29 compn0 30 compp0 31 vcc0 32 cagc0 hmc6545 top view (not to scale) notes 1. exposed pad. exposed pad must be connected to rf/dc ground. 13393-033
data sheet hmc6545 rev. a | page 7 of 23 interface schematics figure 3 . gnd interface schematic figure 4 . inpx, innx interface schematic figure 5 . cagcx interface schematic figure 6 . comppx, compnx interface schematic figure 7 . sda, scl interface schematic figure 8 . outpx, outnx interface schematic figure 9 . regselx interface schematic gnd 13393-002 100? vcc0, vcc1 vcc0, vcc1 inp0, inp1 inn0, inn1 13393-003 cagc0, cagc1 vcc0, vcc1 13393-004 vcc0, vcc1 vcc0, vcc1 compp0, compp1 compn0, compn1 13393-005 vcc0, vcc1 sda/scl 13393-006 vcc0, vcc1 vcc0, vcc1 outp0, outp1 outn0, outn1 50? 50? 13393-007 vcc0, vcc1 regsel0, regsel1 13393-008
hmc6545 data sheet rev. a | page 8 of 23 typical performance characteristics figure 10 . supply current (i dd ) vs. enab led taps over supply voltage figure 11 . supply current (i dd ) vs. enabled taps over enabled channels figure 12 . normalized linearity vs. tap value over temperatur e , tap 4 value is varied , while others are enabled with no ga in figure 13 . supply current vs. enabled taps over t emperature figure 14 . normalized linearity vs. tap val ue over supply voltage , tap 4 value is varied, while others are enabled with no gain figure 15 . thd vs. differential input ampl itude over supply voltage , tap 4 gain is set to +63, while others are enabled with no gain 150 80 90 100 120 140 110 130 0 1 2 3 4 6 8 5 7 9 i dd (ma) enabled taps 3.00v 3.15v 3.30v 3.45v 13393-009 t a = 25c 300 250 200 150 100 50 0 1 2 3 4 6 8 5 7 9 i dd (ma) enabled taps channel 0 channel 0 + channel 1 13393-010 t a = 25c v cc = 3.3v agc = 3 predriver gain = 63 1.0 ?1.0 ?0.6 ?0.2 0.4 0.8 0.2 ?0.8 ?0.4 0 0.6 ?63 ?56 ?49 ?42 ?35 ?28 ?21 ?14 ?7 0 7 14 21 28 35 42 49 56 63 linearity (v/v) tap value +95c +25c ?40c 13393-0 1 1 v cc = 3.3v agc = 3 predriver gain = 63 140 80 90 100 120 110 130 0 1 2 3 4 6 8 5 7 9 i dd (ma) enabled taps +95c +25c ?40c 13393-012 v cc = 3.3v 1.0 ?1.0 ?0.6 ?0.2 0.4 0.8 0.2 ?0.8 ?0.4 0 0.6 ?63 ?56 ?49 ?42 ?35 ?28 ?21 ?14 ?7 0 7 14 21 28 35 42 49 56 63 linearity (v/v) tap value 3.00v 3.15v 3.30v 3.45v 13393-013 t a = 25c agc = 3 predriver gain = 63 12 0 2 4 8 6 10 25 75 125 175 225 375 575 275 475 325 525 425 625 thd (%) differential input amplitude (mv p-p) 3.15v 3.30v 3.45v 13393-014 t a = 25c agc = 2 predriver gain = 63
data sheet hmc6545 rev. a | page 9 of 23 figure 16 . thd vs. differential input amplitu de over temperature , tap 4 gain is set to maximum gain, while others are enabled with no gain figure 17 . thd vs. pre d river gain , tap 4 gain is set to maximum gain, while others are enabled with no gain figure 18 . small signal gain over taps , f or s21 line of each tap , relevant tap is set to maximum gain while remaining taps are enabled with no gain figure 19 . thd vs. differential input amplitude over agc value , tap 4 gain is set to maximum gain, while others are enabled with n o gain figure 20 . differential output amplitu de vs. pre d river gain over agc , input signal : differential prbs 2 31 ? 1, 10 gbps at 500 mv p - p figure 21 . input return loss 12 0 2 4 8 6 10 25 75 125 175 225 375 575 275 475 325 525 425 625 thd (%) differential input amplitude (mv p-p) +95c +25c ?40c 13393-015 v cc = 3.3v agc = 2 predriver gain = 63 7 0 1 2 4 3 5 6 0 7 14 21 28 49 35 42 56 63 thd (%) predriver gain 13393-016 t a = 25c v cc = 3.3v agc = 2 20 ?20 ?16 ?12 4 ?4 12 ?8 8 0 16 0 2 6 10 14 26 18 22 4 8 12 16 20 24 28 30 small signal gain (db) frequency (ghz) tap 0 tap 1 tap 2 tap 3 tap 4 tap 5 tap 6 tap 7 tap 8 13393-017 t a = 25c v cc = 3.3v 12 0 2 4 8 6 10 25 75 125 175 225 375 575 275 475 325 525 425 625 thd (%) differential input amplitude (mv p-p) agc = 2 agc = 3 13393-018 t a = 25c v cc = 3.3v predriver gain = 63 900 0 100 200 400 300 500 700 600 800 0 7 14 21 28 49 35 42 56 63 differential output amplitude (mv p-p) predriver gain setting agc = 0 agc = 4 agc = 7 13393-019 t a = 25c v cc = 3.3v agc = 4 predriver gain = 7 tap 0 = ?3 tap 1 = ?8 tap 2 = ?4 tap 3 = +63 tap 4 = +63 tap 5 = +57 tap 6 = +18 tap 7 = ?41 tap 8 = ?35 0 ?30 ?25 ?20 ?10 ?15 ?5 0 2 6 10 14 26 18 22 4 8 12 16 20 24 28 30 input return loss (db) frequency (ghz) 13393-020 t a = 25c v cc = 3.3v
hmc6545 data sheet rev. a | page 10 of 23 figure 22. output return loss figure 23. typical output wa veform at 22 gbps, prbs 2 31 ? 1 input data, input signal = 300 mv p-p differential figure 24. typical output waveform t 28 gbps, prbs 2 31 ? 1 input data figure 25. typical output wa veform at 10 gbps prbs 2 31 ? 1 input data figure 26. typical output wave form at 25.8 gbps, prbs 2 31 ? 1 input data figure 27. typical output wa veform at 32 gbps, prbs 2 31 ? 1 input data 0 ?30 ?25 ?20 ?10 ?5 ?15 02 6 10 14 26 18 22 4 8 12 16 20 24 28 30 output return loss (db) frequency (ghz) 13393-021 t a = 25c v cc = 3.3v ch3 100mv/div time 10ps/div delay 24.1475ns current minimum maximum total meas jitter rms (f1) 944 f s 944 f s 982 f s 94 jitter p-p (f1) 5.444ps 5.333ps 5.444ps 94 rise time (f1) 16.22ps 18.22ps 18.44ps 94 fall time (f1) 16.22ps 16.00ps 18.67ps 94 13393-022 tap 0 = ?3 tap 1 = +63 tap 2 = ?10 tap 3 = +4 tap 4 = ?1 tap 5 = ?1 tap 6 = ?1 tap 7 = ?1 tap 8 = ?2 agc = 4 predriver gain = 63 ch3 100mv/div time 10ps/div delay 24.1112ns current minimum maximum total meas jitter rms (f1) 1.053ps 1.025ps 1.080ps 125 jitter p-p (f1) 5.557ps 5.333ps 5.567ps 125 rise time (f1) 17.93ps 10.00ps 17.33ps 125 fall time (f1) 17.11ps 16.44ps 17.33ps 125 13393-023 tap 0 = ?3 tap 1 = +63 tap 2 = ?10 tap 3 = +4 tap 4 = ?1 tap 5 = ?1 tap 6 = ?1 tap 7 = ?1 tap 8 = ?2 agc = 4 predriver gain = 63 ch3 100mv/div time 10ps/div delay 24.2003ns current minimum maximum total meas jitter rms (f1) 914 f s 948 f s 4.014ps 236 jitter p-p (f1) 4.880ps 4.000ps 4.889ps 236 rise time (f1) 16.22ps 16.22ps 16.67ps 236 fall time (f1) 18.22ps 17.78ps 16.67ps 236 13393-024 tap 0 = ?3 tap 1 = +63 tap 2 = ?10 tap 3 = +4 tap 4 = ?1 tap 5 = ?1 tap 6 = ?1 tap 7 = ?1 tap 8 = ?2 agc = 4 predriver gain = 63 ch3 100mv/div time 10ps/div delay 24.1468ns current minimum maximum total meas jitter rms (f1) 1.008ps 994 f s 1.021ps 66 jitter p-p (f1) 5.557ps 5.333ps 5.557ps 66 rise time (f1) 17.11ps 16.07ps 17.11ps 66 fall time (f1) 16.69ps 16.44ps 17.11ps 66 13393-025 tap 0 = ?3 tap 1 = +63 tap 2 = ?10 tap 3 = +4 tap 4 = ?1 tap 5 = ?1 tap 6 = ?1 tap 7 = ?1 tap 8 = ?2 agc = 4 predriver gain = 63 ch3 100mv/div time 10ps/div delay 24.0976ns current minimum maximum total meas jitter rms (f1) 960 f s 957 f s 1.036ps 100 jitter p-p (f1) 5.557ps 5.333ps 5.557ps 100 rise time (f1) 15.78ps 15.56ps 15.78ps 100 fall time (f1) 15.56ps 15.56ps 16.08ps 100 13393-026 tap 0 = ?3 tap 1 = +63 tap 2 = ?10 tap 3 = +4 tap 4 = ?1 tap 5 = ?1 tap 6 = ?1 tap 7 = ?1 tap 8 = ?2 agc = 4 predriver gain = 63
data sheet hmc6545 rev. a | page 11 of 23 theory of operation the hmc6545 advanced lin ear equalizer has two symmetrical channels , each containing an input agc, a 9 - tap delay chain with each delay tap connected to a variable tap amplifier, a summation node combining the outputs of the tap amplifiers, and an output driver. input receiver agc the hmc6545 has an integrated agc that linearly amplifies/ attenuates the input signal , generating a fixed voltage swing level for further processing in the ffe delay line. an input agc is requi red both to supply a well defined voltage swing level to the ffe delay line and to control the internal and external (output) voltage swings because the signal path is linear. the agc has a sensitivity level of 40 mv p - p differential. the hmc6545 processes the input signal linearly at up to a 600 mv p - p differential input voltage level . the agc loop bandwidth and settling time can be changed using an external capacitor connected to the cagc0 /gnd and cagc1/ gnd nodes. an internal 2.5 p f capacitor at th ese node s sets the d efault agc settling time to 0.5 s. the evaluation board includes 1 nf capacitors for both channels. internal and external offset correction circuitry the input receiver has two modes of offset correction t hat can be configured by changing the offset settings register via the 2 - wire interface : automatic offset correction and manual offset correction (all registers in table 5 are identical to each other) . table 5 . offset settings registers register description reg ister 0x0a channel 0 offset settings, array a r egister register 0x2a channel 0 offset settings, array b r egister register 0x4a channel 1 offset settings, array a r egister register 0x6a channel 1 offset settings , array b r egister by default, the input receiver is configured in the automatic offset correction mode , which can correct up to 60 mv of input referred dc offset at the worst case agc gain (maximum agc gain with a minimum input signal level). the input referred automatic offset correction range changes depending on the agc gain and increases up to 180 mv for minimum agc gain with a maximum signal level at the input of the receiver. automatic offset correction loop bandwidth is externally set by a series rc network (for each channel, r1 / c1 and r2 / c2) , and it is recommended to keep the component values as shown in the evaluation board schematic (see figure 35). for channel 1, array a, a utomatic offset correction loop can be disabled by setting register 0x4a , bit 6 to 0, which enables the manual offset correction (set register 0x0a for channel 0, array a ; register 0x2a for channel 0, array b; and register 0x6a for channel 1, array b; see table 5 ) . manual offset correction amount can be adjusted by configuring reg ister 0x4a , bits[5:0] , where reg ister 0x4a , bit 5 defines the sign and bits [4:0] define the magnitude of gain (see table 48) . similar to automatic offset correction mode, manual offset correction dynamic range changes with the agc gain with the total correction being 60 mv for maximum agc gain , which corresponds to about 2 mv/step (5 - bit control) adjustment resolution for maximum agc gain. for minimum agc gain, the correction dynamic range increases to 180 mv, and the minimum step for adjustment increases to 6 mv/step . ffe delay line t he ffe delay line receives an input signal from the agc (with a controlled magnitude) , and this signal propagates along a delay line composed of eight delay elements , where each delay element has 18 ps nominal propagation . the delayed signals are then mult iplied by programmable coefficients by the tap amplifiers and summed together. one of the taps near the center can be selected a s the main tap. the t aps that follow are called post cursor taps, and the t aps that precede are called pre cursor taps. by combining different tap values, a wide variety of filter transfer functions can be created that can, for example, compensate for the gain or phase distortion of a lossy channel or the chromatic dispersion of an optical channel. tap amplifier gains are cont rolled using the 2 - wire interface with five bits of magnitude resolution with positive or negative polarity. to disable a coefficient, set the gain of the particular tap amplifier to 0 (positive gain sign, and 0 gain setting). in addition, the tap amplifie r can be powered down to save power , but this may have an impact on the delay and gain of the remaining taps in the delay chain. see table 14 to table 22 and table 38 to table 46 for array a tap amplifier settings for channel 0 and channel 1, respectively. for array b tap amplifier settings, see table 26 to table 34 and table 50 to table 58 for channel 0 and channel 1, respectively. each channel has two sets of tap coefficient register arrays (channel 0 , array a ; channel 0 , array b ; channel 1, array a; and channel 1 , array b) that can be configured through the 2 - wire interface . register 0x00 to reg ister 0x08 set the tap coefficients of channel 0 , array a. register 0x20 to reg ister 0x28 set the tap coeffi cients of channel 0 , array b. reg ister 0x40 to reg ister 0x48 set the tap coefficients of channel 1 , array a. reg ister 0x60 to reg ister 0x68 set the tap coefficients of channel 1 , array b . the regsel0 and regsel1 pins of the device set the default register array (a or b) , determining the tap coefficients of a particular channel. for example, applying regsel0 = 0 activates channel 0, array a ; and regsel1 = 0 activates channel 1 , array a . a pplying regsel0 = 1 activates channel 0 , array b ; and regsel1 = 1 activates channel 1 , array b .
hmc6545 data sheet rev. a | page 12 of 23 output driver after the tap amplifier outputs are summed, the combined signal is received by a linear output driver. the output driver consists of two stages . t he first stage is a predriver stage providing contr ollable signal amplification (6 - bit resolution) using reg ister 0x09 (channel 0 , array a), reg ister 0x29 (channel 0 , array b), reg ister 0x49 (channel 1 , array a), and reg ister 0x69 (channel 1 , array b). similar to the tap coefficient registers, each predriver has t wo registers that can be selected asynchro - nously by the regsel0 and regsel1 pins . the register values must be configured through the 2 - wire interface prior to the register selection via the regsel0 and regsel1 pins . see table 7 to table 10 for the predriver settings for channel 0 and channel 1 . the final stage o f the output driver is a 50 ? cml driver stage that provides the specified linearity (according to the thd specification) up to 600 mv p - p differential output swing. the linearity degrades at higher output swings. 2 - wire serial port to access all of its internal registers, the hmc6545 uses a 2 - wire interface, which consists of a serial data line (sda) and a serial clock line (scl). both sda and scl are implemented with open - drain input/outp ut pins and are connected to a positive supply voltage via pull - up resistors. typically, a microcontroller, a microprocessor or a digital signal processor acts as a master, controls the bus, and has the responsibil - ity to generate the clock signal and devi ce addresses. the hmc6545 functions as a slave device. the device address on the hmc6545 is 0x38 (default) and set by connecting the regsel0 and regsel1 pins to either v cc (logic 1) or gnd (logic 0) and by writing 1 to register 0x80, bit 6. if register 0x80, bit 6 = 0 (default), the regsel0 and regsel1 pins select array a or array b. if register 0x80, bit 6 = 1, the regsel0 and regsel1 pins also determine the 2 - wire interface device address according to table 6 . table 6 . 2 - wire interface device address setting regsel1 regsel0 address setting (register 0 x 80, bit 6 = 1) 0 0 0x38 (default) 0 1 0x39 1 0 0x3a 1 1 0x3b table 7 . register 0x09 channel 0 predriver settings , array a register bits type name default minimum maximum description [5:0] r/w pre d river g ain 0x30 000000 111111 channel 0 predriver gain [7:6] r/w factory s et 0b00 not u sed table 8 . register 0x29 channel 0 predriver settings , array b register bits type name default minimum maximum description [5:0] r/w predriver gain 0x3f 000000 111111 channel 0 predriver gain [7:6] r/w factory set 0b00 not used table 9 . register 0x49 channel 1 predriver settings , array a register bits type name default minimum maximum description [5:0] r/w predriver gain 0x30 000000 111111 channel 1 predriver gain [7:6] r/w factory set 0b00 not used table 10. register 0x69 channel 1 predriver settings , array b register bits type name default minimum maximum description [5:0] r/w predriver gain 0x3f 000000 111111 channel 1 predriver gain [7:6] r/w factory set 0b00 not used
data sheet hmc6545 rev. a | page 13 of 23 protocol table 11 lists the definitions and conditions occurring in a 2 - wire data transfer. figure 28 s hows a representation of a complete communication cycle on the 2 - wire interface. the master generates a s tart condition to indicate the beginning of a new data transfer. the master then starts generating clock pulses on scl and transmits the first byte on sda. this first byte always consists of a 7 - bit slave address followed by one bit that indicates the r ead/ w rite direction (r/ w ) . the device on the bus with a matching address generates an acknowledge. the master continues generating more clock pulses on scl and, depending on the value of the r/w bit, sends ( write operation, r/ w = 0) or receives ( r ead operation, r/ w = 1) data on sda. in each case , the receiver must acknowledge the data sent by the transmitter. this sequence of 8 - bit data followed by a 1 - bit acknowledge can be repeated multiple times. when all data communication is over for the current transfer cycle , the master indicates the end of data transfer by generating a s top condition. data transfer formats wr ite cy cle in a write cycle, the master transmitter sends data to the slave receiver. the transfer direction is from master to slave and does not change ( see figure 29 ). the master generates a start condition followed by a 7 - bit slave address and by the r/ w bit set to 0. the slave with a matching address replies with an acknowledge. the master then transmits the first byte to the slave device. this first byte is an address of the internal registers of the slave. the slave device replies with an acknowledge bit. for a subsequent r ead cycl e, the master generates a stop bit; otherwise, the master then transmits the next byte, which is a data byte to be stored in the internal slave register previously addressed. this data byte is followed by an acknowledge bit from the slave. this process can continue for multiple bytes , and the slave device increments its internal register address count as it receives subsequent bytes from the master. when all data transfer is over, the master generates a s top condition to end the cycle. table 11. 2 - wire data transfer terminology a nd definitions term definition start a start condition is always generated by the master and is defined as a high to l ow transition on the sda line while scl is h igh. the bus becomes busy after a start condition. stop a stop condition is always generated by the master and is defined as a l ow to h igh transition on the sda line while scl is h igh. the bus becomes free afte r the stop condition occurs. byte format every b yte transmitted on sda must be eight bits long and is transferred with the m ost s ignificant b it (msb) first. e ach byte must be followed by an a cknowledge bit. data valid condition for data to be considered valid, the sda line must be stable during the entire high period of its respective clock pulse. acknowledge for each byte sent or received on the bus , the master generates an extra clock cycle that is used for acknowledgement, for a total of nine bits. t he transmitter releases the sda line, which is pulled h igh by the external resistor, and the receiver must pull down the sda line and drive it l ow while scl is h igh during this entire clock cycle to indicate acknowledgment. sda is left h igh during this clo ck cycle to indicate a n o acknowledge (nack) situation, usually because the device addressed is unable to receive or transmit the data requested. figure 28 . complete data transfer figure 29 . write cycle 1 2 7 8 9 7 8 9 1 2 7 8 9 1 2 sda scl start condition stop condition msb address data ack ack data ack r/w 13393-027 start r/w = 0 ack ack stop nack data byte ack address byte data byte slave address from master t o sl a ve from sl a ve t o master 13393-028
hmc6545 data sheet rev. a | page 14 of 23 read cycle in a read cycle, the master reads from the slave immediately after the first byte. the direction of data transfer changes between master and slave (see figure 32) . in this case , the r/ w bit is set to 1 to indicate that the master read s data from the slave device. the address of the internal register from which the data is to come h as been previously set in a precedent w rite cycle ; otherwise , the slave device defaults to address 0 x00 . this time , the slave device transmits all the data bytes and the master replies with an acknowledge bit. for the last byte read, the master replies with a no acknowledge bit to indicate to the slave that it must stop transmitting data. the master then generates a s top condition , and the cycle ends. 2 - wire interface design considerations the hmc6545 2 - wire interface slave interface responds to any register address or data matching its chip address even when there is no preceding start condition . a 2 - wire interface communication is defined as shown in figure 30. figure 30 . 2 - wire interface commun i cation coincidentally , the data or register address can be the same as the chip address of another device on the same bus. however, that other device does not respond because there is no preceding start condition . in the hmc6545 , regardless of whether ther e is a start condition , if the hmc6545 sees a bit stream that corresponds to its chip address, it then responds and causes unwanted results . t here must be only one hmc6545 device on the 2 - wire interface bus ; otherwise, 2 - wire interface bus multiplexers can be used to isolate the hmc6545 devices. see figure 33 for an example design. reset a low strobe signal must be sent to the rst pin to reset the registers to their default value s. sda and scl must be high in the 2 - wire interface bus before and after the rising edge. figure 31 . reset registers figure 32 . read cycle figure 33 . multiple hmc6545 devices on 2- wire interface bus 13393-034 start chip address + write address byte data byte stop start chip address + read data byte stop sda scl rst 0.5s 0.5s 1.0s 13393-031 start r/w = 1 ack ack stop nack data byte ack data byte data byte slave address from master t o sl a ve from sl a ve t o master 13393-029 master hmc6545 hmc6545 2-wire interface bus demux control other vendor slave1 other vendor slave2 13393-030 2-wire interface bus 2-wire interface bus
data sheet hmc6545 rev. a | page 15 of 23 register map register list summary and register descrip tions global register global register bit order is different for read and write operations. table 12. reg ister 0x80 global register, write operation bit type name default description 7 w factory set 0 not used. 6 w 2 - wire interface device address read 0 2 - wire interface device address set. writing 1 generates a 2 - wire interface device address read command. 5 w channel 1 enable 1 channel 1 enable. writing 1 enables channel 1. 4 w channel 0 enable 1 channel 0 enable. writing 1 enables channel 0. 3 w factory set 1 not used. 2 w channel 1 reset 1 channel 1 soft reset. writing 0 generates a soft reset, resetting all the registers in channel 1 to their default states. writing 1 resumes normal chip operation. 1 w channel 0 reset 1 channel 0 soft reset. writing 0 generates a soft reset, resetting all the registers in channel 0 to th eir default states. writing 1 resumes normal chip operation. 0 w global r eset 1 global s oft r eset. wri ting 0 generates a soft reset , resetting all the registers to their default states. writing 1 resumes normal chip operation. table 13. register 0x80 global register, read operation bit type name default description 7 r 2 - wire interface device address, bit 1 0 bit 1 of device address 6 r 2 - wire interface device address, bit 0 0 least significant bit of device address 5 r factory set not applicable not used 4 r channel 1 enable 1 channel 1 enable 3 r channel 0 enable 1 channel 0 enable 2 r factory set not applicable not used 1 r channel 1 reset 1 channel 1 reset 0 r factory s et 0 not used channel 0 , array a register set table 1 register 0x00 channel 0 , ta 0 settings , array a register bit type name default description 7 r/w tap 0 enable 1 channel 0 tap 0 enable. 6 r/w tap 0 gain sign 1 channel 0 tap 0 gain sign. 1 means positive, 0 means negative. [5:0] r/w tap 0 g ain 0x00 channel 0 tap 0 g ain . table 15. register 0x01 channel 0 , tap 1 settings , array a register bit type name default description 7 r/w tap 1 enable 1 channel 0 tap 1 enable. 6 r/w tap 1 gain sign 1 channel 0 tap 1 gain sign. 1 means positive, 0 means negative. [5:0] r/w tap 1 g ain 0x00 channel 0 tap 1 g ain . table 16. register 0x02 channel 0 , tap 2 settings , array a register bit type name default description 7 r/w tap 2 enable 1 channel 0 tap 2 enable. 6 r/w tap 2 gain sign 1 channel 0 tap 2 gain sign. 1 means positive, 0 means negative. [5:0] r/w tap 2 gain 0x00 channel 0 tap 2 g ain .
hmc6545 data sheet rev. a | page 16 of 23 table 17. register 0x03 channel 0 , tap 3 settings , array a register bit type name default description 7 r/w tap 3 enable 1 channel 0 tap 3 enable. 6 r/w tap 3 gain sign 1 channel 0 tap 3 gain sign. 1 means positive, 0 means negative. [5:0] r/w tap 3 gain 0x00 channel 0 tap 3 g ain . table 18. register 0x04 channel 0 , tap 4 settings , array a register bit type name default description 7 r/w tap 4 enable 1 channel 0 tap 4 enable. 6 r/w tap 4 gain sign 1 channel 0 tap 4 gain sign. 1 means positive, 0 means negative. [5:0] r/w tap 4 gain 0x3f channel 0 tap 4 g ain . table 19. register 0x05 channel 0 , tap 5 settings , array a register bit type name default description 7 r/w tap 5 enable 1 channel 0 tap 5 enable. 6 r/w tap 5 gain sign 1 channel 0 tap 5 gain sign. 1 means positive, 0 means negative. [5:0] r/w tap 5 gain 0x00 channel 0 tap 5 g ain . table 20. register 0x06 channel 0 , tap 6 settings , array a register bit type name default description [5:0] r/w tap 6 gain 0x00 channel 0 tap 6 g ain . 6 r/w tap 6 gain sign 1 channel 0 tap 6 g ain s ign. 1 means positive, 0 means negative. 7 r/w tap 6 enable 1 channel 0 tap 6 e nable . table 21. register 0x07 channel 0 , tap 7 settings , array a register bit type name default description 7 r/w tap 7 enable 1 channel 0 tap 7 enable. 6 r/w tap 7 gain sign 1 channel 0 tap 7 gain sign. 1 means positive, 0 means negative. [5:0] r/w tap 7 gain 0x00 channel 0 tap 7 g ain . table 22. register 0x08 channel 0 , tap 8 settings , array a register bit type name default description 7 r/w tap 8 enable 1 channel 0 tap 8 enable. 6 r/w tap 8 gain sign 1 channel 0 tap 8 gain sign. 1 means positive, 0 means negative. [5:0] r/w tap 8 gain 0x00 channel 0 tap 8 gain . table 23. register 0x09 channel 0 pre d river settings , array a register bit type name default description [7:6] r/w factory set 0b00 not used [5:0] r/w pre d river gain 0x30 channel 0 p re d river g ain table 24. register 0x0a channel 0 offset settings , array a register bit type name default description 7 r/w factory set 0 not used 6 r/w automatic offset enable 1 channel 0 automatic offset enable 5 r/w manual offset sign 0 channel 0 manual offset sign [4:0] r/w manual offset gain 0x00 channel 0 manual offset gain table 25. register 0x0b channel 0 internal agc amplitude , array a register bit type name default description [7:3] r/w factory set 0x00 not used [2:0] r/w internal agc amplitude 0b100 internal agc a mplitude
data sheet hmc6545 rev. a | page 17 of 23 channel 0 , array b register set table 26. register 0x20 channel 0 , tap 0 settings, array b register bit type name default description 7 r/w tap 0 enable 1 channel 0 tap 0 enable. 6 r/w tap 0 gain sign 1 channel 0 tap 0 gain sign. 1 means positive, 0 means negative. [5:0] r/w tap 0 g ain 0x00 channel 0 tap 0 g ain . table 27. register 0x21 channel 0 , tap 1 settings , array b register bit type name default description 7 r/w tap 1 enable 1 channel 0 tap 1 enable. 6 r/w tap 1 gain sign 0 channel 0 tap 1 gain sign. 1 means positive, 0 means negative. [5:0] r/w tap 1 gain 0x04 channel 0 tap 1 g ain . table 28. register 0x22 channel 0 , tap 2 settings , array b register bit type name default description 7 r/w tap 2 enable 1 channel 0 tap 2 enable. 6 r/w tap 2 gain sign 1 channel 0 tap 2 gain sign. 1 means positive, 0 means negative. [5:0] r/w tap 2 g ain 0x3f channel 0 tap 2 g ain . table 29. register 0x23 channel 0 , tap 3 settings , array b register bit type name default description 7 r/w tap 3 enable 1 channel 0 tap 3 enable. 6 r/w tap 3 gain sign 0 channel 0 tap 3 gain sign. 1 means positive, 0 means negative. [5:0] r/w tap 3 g ain 0x28 channel 0 tap 3 g ain . table 30. register 0x24 channel 0 , tap 4 settings , array b register bit type name default description 7 r/w tap 4 enable 1 channel 0 tap 4 enable. 6 r/w tap 4 gain sign 0 channel 0 tap 4 gain sign. 1 means positive, 0 means negative. [5:0] r/w tap 4 g ain 0x04 channel 0 tap 4 g ain . table 31. register 0x25 channel 0 , tap 5 settings , array b register bit type name default description 7 r/w tap 5 enable 1 channel 0 tap 5 enable. 6 r/w tap 5 gain sign 1 channel 0 tap 5 gain sign. 1 means positive, 0 means negative. [5:0] r/w tap 5 g ain 0x00 channel 0 tap 5 g ain . table 32. register 0x26, channel 0 , tap 6 settings , array b register bit type name default description 7 r/w tap 6 enable 1 channel 0 tap 6 enable. 6 r/w tap 6 gain sign 1 channel 0 tap 6 gain sign. 1 means positive, 0 means negative. [5:0] r/w tap 6 g ain 0x00 channel 0 tap 6 g ain . table 33. register 0x27 channel 0 , tap 7 settings , array b register bit type name default description 7 r/w tap 7 enable 1 channel 0 tap 7 enable. 6 r/w tap 7 gain sign 1 channel 0 tap 7 gain sign. 1 means positive, 0 means negative. [5:0] r/w tap 7 g ain 0x00 channel 0 tap 7 g ain . table 34. register 0x28 channel 0 , tap 8 settings , array b register bit type name default description 7 r/w tap 8 enable 1 channel 0 tap 8 enable. 6 r/w tap 8 gain sign 1 channel 0 tap 8 gain sign. 1 means positive, 0 means negative. [5:0] r/w tap 8 g ain 0x00 channel 0 tap 8 g ain .
hmc6545 data sheet rev. a | page 18 of 23 table 35. register 0x29 channel 0 pre d river settings , array b register bit type name default description [7:6] r/w factory set 0b00 not used [5:0] r/w pre driver gain 0x3f channel 0 pre driver gain table 36. register 0x2a channel 0 offset settings , array b register bit type name default description 7 r/w factory set 0 not used 6 r/w automatic offset enable 1 channel 0 automatic offset enable 5 r/w manual offset sign 0 channel 0 manual offset sign [4:0] r/w manual offset gain 0x00 channel 0 manual offset gain table 37. register 0x2b channel 0 internal agc amplitude , array b register bit type name default description [7:3] r/w factory set 0x00 not used [2:0] r/w internal agc amplitude 0b100 internal agc amplitude channel 1 , array a register set table 38. register 0x40 channel 1 , tap 0 settings , array a register bit type name default description 7 r/w tap 0 enable 1 channel 1 tap 0 enable. 6 r/w tap 0 gain sign 1 channel 1 tap 0 gain sign. 1 means positive, 0 means negative. [5:0] r/w tap 0 gain 0x00 channel 1 tap 0 gain . table 39. register 0x41 channel 1 , tap 1 settings , array a register bit type name default description 7 r/w tap 1 enable 1 channel 1 tap 1 enable. 6 r/w tap 1 gain sign 1 channel 1 tap 1 gain sign. 1 means positive, 0 means negative. [5:0] r/w tap 1 gain 0x00 channel 1 tap 1 gain . table 40. register 0x42 channel 1 , tap 2 settings , array a register bit type name default description 7 r/w tap 2 enable 1 channel 1 tap 2 enable. 6 r/w tap 2 gain sign 1 channel 1 tap 2 gain sign. 1 means positive, 0 means negative. [5:0] r/w tap 2 gain 0x00 channel 1 tap 2 gain . table 41. register 0x43 channel 1 , tap 3 settings , array a register bit type name default description 7 r/w tap 3 enable 1 channel 1 tap 3 enable. 6 r/w tap 3 gain sign 1 channel 1 tap 3 gain sign. 1 means positive, 0 means negative. [5:0] r/w tap 3 gain 0x00 channel 1 tap 3 gain . table 42. register 0x44 channel 1 , tap 4 settings , array a register bit type name default description 7 r/w tap 4 enable 1 channel 1 tap 4 enable. 6 r/w tap 4 gain sign 1 channel 1 tap 4 gain sign. 1 means positive, 0 means negative. [5:0] r/w tap 4 gain 0x1f channel 1 tap 4 gain . table 43. register 0x45 channel 1 , tap 5 settings , array a register bit type name default description 7 r/w tap 5 enable 1 channel 1 tap 5 enable. 6 r/w tap 5 gain sign 1 channel 1 tap 5 gain sign. 1 means positive, 0 means negative. [5:0] r/w tap 5 gain 0x00 channel 1 tap 5 ga in .
data sheet hmc6545 rev. a | page 19 of 23 table 44. register 0x46 channel 1 , tap 6 settings , array a register bit type name default description 7 r/w tap 6 enable 1 channel 1 tap 6 enable. 6 r/w tap 6 gain sign 1 channel 1 tap 6 gain sign. 1 means positive, 0 means negative. [5:0] r/w tap 6 gain 0x00 channel 1 tap 6 gain . table 45. register 0x47 channel 1 , tap 7 settings , array a register bit type name default description 7 r/w tap 7 enable 1 channel 1 tap 7 enable. 6 r/w tap 7 gain sign 1 channel 1 tap 7 gain sign. 1 means positive, 0 means negative. [5:0] r/w tap 7 gain 0x00 channel 1 tap 7 gain . table 46. register 0x48 channel 1 , tap 8 settings , array a register bit type name default description 7 r/w tap 8 enable 1 channel 1 tap 8 enable. 6 r/w tap 8 gain sign 1 channel 1 tap 8 gain sign. 1 means positive, 0 means negative. [5:0] r/w tap 8 gain 0x00 channel 1 tap 8 gain . table 47. register 0x49 channel 1 pre d river settings , array a register bit type name default description [7:6] r/w factory set 0b00 not used [5:0] r/w pre driver gain 0x30 channel 1 predriver gain table 48. register 0x4a channel 1 offset settings , array a register bit type name default description 7 r/w factory set 0 not used 6 r/w automatic offset enable 1 channel 0 automatic offset enable 5 r/w manual offset sign 0 channel 0 manual offset sign [4:0] r/w manual offset gain 0x00 channel 0 manual offset gain table 49. register 0x4b channel 1 internal agc amplitude , array a register bit type name default description [7:3] r/w factory set 0x00 not used [2:0] r/w internal agc amplitude 0b100 internal agc amplitude channel 1 , array b register set table 50. register 0x60 channel 1 , tap 0 settings , array b register bit type name default description 7 r/w tap 0 enable 1 channel 1 tap 0 enable. 6 r/w tap 0 gain sign 1 channel 1 tap 0 gain sign. 1 means positive, 0 means negative. [5:0] r/w tap 0 gain 0x00 channel 1 tap 0 gain . table 51. register 0x61 channel 1 , tap 1 settings , array b register bit type name default description 7 r/w tap 1 enable 1 channel 1 tap 1 enable. 6 r/w tap 1 gain sign 0 channel 1 tap 1 gain sign. 1 means positive, 0 means negative. [5:0] r/w tap 1 gain 0x04 channel 1 tap 1 gain . table 52. register 0x62 channel 1 , tap 2 settings , array b register bit type name default description 7 r/w tap 2 enable 1 channel 1 tap 2 enable. 6 r/w tap 2 gain sign 1 channel 1 tap 2 gain sign. 1 means positive, 0 means negative. [5:0] r/w tap 2 gain 0x3f channel 1 tap 2 gain .
hmc6545 data sheet rev. a | page 20 of 23 table 53. register 0x63 channel 1 , tap 3 settings , array b register bit type name default description 7 r/w tap 3 enable 1 channel 1 tap 3 enable. 6 r/w tap 3 gain sign 0 channel 1 tap 3 gain sign. 1 means positive, 0 means negative. [5:0] r/w tap 3 gain 0x28 channel 1 tap 3 g ain . table 54. register 0x64 channel 1 , tap 4 settings , array b register bit type name default description 7 r/w tap 4 enable 1 channel 1 tap 4 enable. 6 r/w tap 4 gain sign 0 channel 1 tap 4 gain sign. 1 means positive, 0 means negative. [5:0] r/w tap 4 gain 0x04 channel 1 tap 4 g ain . table 55. register 0x65 channel 1 , tap 5 settings , array b register bit type name default description 7 r/w tap 5 enable 1 channel 1 tap 5 enable. 6 r/w tap 5 gain sign 1 channel 1 tap 5 gain sign. 1 means positive, 0 means negative. [5:0] r/w tap 5 gain 0x00 channel 1 tap 5 gain . table 56. register 0x66 channel 1 , tap 6 settings , array b register bit type name default description 7 r/w tap 6 enable 1 channel 1 tap 6 enable. 6 r/w tap 6 gain sign 1 channel 1 tap 6 gain sign. 1 means positive, 0 means negative. [5:0] r/w tap 6 gain 0x00 channel 1 tap 6 gain . table 57. register 0x67 channel 1 , tap 7 settings , array b register bit type name default description 7 r/w tap 7 enable 1 channel 1 tap 7 enable. 6 r/w tap 7 gain sign 1 channel 1 tap 7 gain sign. 1 means positive, 0 means negative. [5:0] r/w tap 7 gain 0x00 channel 1 tap 7 gain . table 58. register 0x68 channel 1 , tap 8 settings , array b register bit type name default description 7 r/w tap 8 enable 1 channel 1 tap 8 enable. 6 r/w tap 8 gain sign 1 channel 1 tap 8 gain sign. 1 means positive, 0 means negative. [5:0] r/w tap 8 gain 0x00 channel 1 tap 8 g ain . table 59. register 0x69 channel 1 predriver settings , array b register bit type name default description [7:6] r/w factory set 0b00 not used [5:0] r/w pre driver gain 0x3f channel 1 predriver gain table 60. register 0x6a channel 1 offset settings , array b register bit type name default description 7 r/w factory set 0 not used 6 r/w automatic offset enable 1 channel 1 automatic offset enable 5 r/w manual offset sign 0 channel 1 manual offset sign [4:0] r/w manual offset gain 0x00 channel 1 manual offset gain table 61. register 0x6b channel 1 internal agc amplitude , array b register bit type name default description [7:3] r/w factory set 0x00 not used [2:0] r/w internal agc amplitude 0b100 internal agc amplitude
data sheet hmc6545 rev. a | page 21 of 23 evaluation p rinted c ircuit b oard (pcb) figure 34 . pcb evaluation kit contents the hmc6545 evaluation pcb kit, ekit01 - hmc6545lp5 , includes the following components: ? 6 - foot usb 2.0 , type a male to type b male cable ? user software cd - rom the cd - rom contains user software, an evaluation pcb schematic, and a user manual. to order the evaluation kit, see the ordering guide section . 21 20 scl 3.3v sda j10 gnd r16 r15 r23 r24 r22 40 c17 u11 c18 outp1 c14 u5 c13 inn0 inp0 outn0 c16 c15 tp1 +5v gnd +3.3v c30 vcc0 r18 tp5 c27 c29 c28 c25 u2 c26 c33 r8 c24 c23 gnd sw1 u1 j1 j2 j3 j4 j5 j6 j7 j8 tp2 tp4 tp3 u7 outp0 u4 1 r11 c19 u6 c20 inp1 j9 inn1 tp6 tp7 svcc vcc1 outn1 c37 c36 c34 r17 r12 tp8 vdd1 r13 r14 r10 13393-032
hmc6545 data sheet rev. a | page 22 of 23 figure 35 . evaluation board schematic 2. rf differential pairs are matched length: inp0/inp1, inn0/inn1, outp0/outp1, outn0/outn1. thru cal place caps close to vcc0 pin 31 on u1 place caps & l close to vcc1 pin 16 on u1 place caps & l close to svcc pin on u1 place c21 close to cagcb pin place c22 close to cagca pin place caps & l close to vcc0 pin 25 on u1 place caps close to vcc1 pin 10 on u1 notes: 1. rf traces are 50 ohm impedance: inp0/inp1, inn0/inn1, outp0/outp1, outn0/outn1. j6 k_sri-ns k_sri-ns j5 c17 100nf c40 100nf k_sri-ns j8 k_sri-ns j7 k_sri-ns j1 c10 100pf k_sri-ns j2 c14 c16 100nf k_sri-ns j4 c18 100nf k_sri-ns j3 r6 3.3k? c21 1nf 1k? r2 c2 1nf r5 1.69k? r1 1k 1nf c22 c12 100pf c11 100nf j9 tsm-102-01-l-dv 2 4 3 1 r3 10k? c1 1nf r4 10k? c4 100pf c3 100nf c6 100pf c5 100pf c9 100pf c8 100pf c7 100pf c20 100nf l1 27nh l2 27nh c19 100nf l3 27nh tp6 r19 1k? tp7 r20 1k? tp5 r21 1k? u1 hmc6545 27 32 26 22 25 21 15 16 14 13 12 11 10 9 17 18 23 24 19 20 28 29 30 31 8 7 6 2 1 5 4 3 comppa compna rst rgsel0 cagca rgsel1 vcc0 inn0 inp0 inp1 inn1 gnd gnd gnd gnd outp1 outp0 outn1 outn0 gnd gnd gnd gnd vcc0 c15 100nf j11 k_sri-ns j12 k_sri-ns c41 100nf c38 100nf j13 k_sri-ns j14 k_sri-ns c13 100nf c39 100nf scl rst vcc1 vcc1 vcc0 vcc0 outp0 outn0 outp1 outn1 inp0 inn0 inp1 inn1 3.3v 3.3v 3.3v svcc svcc svcc rgsel0 rgsel1 sda thru_cal_rfp thru_cal_rfn cagcb comppb compnb sda svcc vcc1 vcc1 scl 100nf 13393-035
data sheet hmc6545 rev. a | page 23 of 23 outline dimensions figure 36 . 32 - lead lead frame ch ip scale package [lfcsp] 5 mm 5 mm body and 0.90 mm package height (hcp - 32 - 1) dimensions shown in millimeters ordering guide model temperature range package description lead finish msl rating 1 package marking 2 package option hmc6545lp5e ?40c to + 95c 32 - lead lead frame chip scale package [lfcsp] 100% matte sn msl1 xxxx 6545 h hcp -32 -1 hmc6545lp5etr ?40c to +95c 32 - lead lead frame chip scale package [lfcsp] 100 matte sn msl1 xxxx 6545 h hcp -32 -1 ekit01 - hmc6545lp5 evaluation kit 1 max imum peak reflow temperature of 260 c . 2 xxxx is the four - d igit lot number . 03-04-2015- a 1 0.50 bsc bot t om view top view pin 1 indic a t or 32 9 16 17 24 25 8 exposed pa d pin 1 indic a t or sea ting plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.25 0.18 5.10 5.00 sq 4.90 1.00 0.90 0.80 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.45 0.40 0.35 0.20 min 3.80 3.65 sq 3.50 compliant to jedec standards mo-220- vhhd-4 . pkg-000000 3.50 ref ? 2015 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d13393 - 0 - 10/15(a)

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